Overview
About the program is compiled and linked
Compile time, the compiler needs is the correct syntax, functions, and variable declaration is correct. For the latter, usually you need to tell the compiler header file location (should only be declared in the header file, but should be defined in C / C + + files), as long as all the proper syntax compiler can compile the intermediate target files. In general, each source file should correspond to an intermediate object files (O files, or OBJ files).
Link, mainly linked functions and global variables, so we can use these intermediate object files (O files, or OBJ files) to link our application. Linker and regardless of the source file where the function, although the function of an intermediate object files (Object File), most of the time, because too many source files, the compiler generates an intermediate object files too, and in the need to clearly point out the link among target file name, which is very convenient for the compiler, so we have to give the intermediate target pack files, in Windows, this package is called "library" (Library File), that is. lib files under UNIX, is Archive File, that is. a file.
In summary, the source file will first generate intermediate target file, and then from the middle of the target file to generate executable file. At compile time, the compiler detects only program syntax, and functions, whether the variable is declared. If the function is not declared, the compiler will give a warning, but can generate Object File. In the linker, the linker will find all of the Object File in the implementation of the function, if not, it will be reported to the link error code (Linker Error), the VC, this error is usually: Link 2001 error, saying that that the linker can not find the function implementation. You need to specify the function Object File.
Well, get, GNU's make lots of stuff, without further ado, let us begin.
Makefile describes
make command is executed, you need a Makefile to tell how to make command required to compile and link the program.
First, we use an example to illustrate the Makefile rules of writing. In order to give you a sense of Xing understanding. This example comes from the GNU make manual, in this example, we have eight C project files, header files, and 3, we write a Makefile to tell how to make command to compile and link these files. Our rules are:
As long as our Makefile written good enough, all of this, we only use a make command can be completed, make command automatically intelligently according to the current file modification to determine which files need to be recompiled, and thus need to compile program files and link targets.
1. Makefile rules
In about this Makefile before, let us first take a cursory look at the Makefile rules.
target ...: Prerequisites ...
command
...
...
target that is a target file, which can be Object File, it can be executed files. Can also be a label (Label), the label of this feature, in the subsequent "pseudo target" will be described in the chapter.
prerequisites that is, to generate the required files that target or targets.
command is the make command to be executed. (Arbitrary Shell Command)
This is a file dependencies, ie, target the one or more target file depends on prerequisites in the document, and its generation rules defined in the command. White said that, prerequisites, if there is more than one file is newer than the target file, then, command defined commands will be executed. This is the Makefile rules. That is the core content of the Makefile.
In the final analysis, Makefile is such a thing that seems to me also that the end of this document. Oh. Not really, this is the main line of the Makefile and the core, but not enough to write a Makefile, I will back little by little work experience combined with my coming to you slowly. Content still living. :)
2. Sample
As previously mentioned, if a project has three header files, and eight C files, we described earlier in order to complete the three rules, we Makefile would look like this below.
edit: main.o kbd.o command.o display.o /
insert.o search.o files.o utils.o
CC-O edit main.o kbd.o command.o display.o /
insert.o search.o files.o utils.o
main.o: main.c defs.h
CC-c main.c
kbd.o: kbd.c defs.h command.h
CC-c kbd.c
command.o: COMMAND.C defs.h command.h
CC - c COMMAND.C
display.o: display.c defs.h buffer.h
CC-c display.c
insert.o: insert.c defs.h buffer.h
CC-c insert.c
search.o: search.c defs . h buffer.h
CC-c search.c
files.o: modifier for defs.h buffer.h command.h
CC-c modifier for
utils.o: utils.c defs.h
CC-c utils.c
clean :
RM edit main.o kbd.o command.o display.o /
insert.o search.o files.o utils.o
Slash (/) is a newline mean. This is more convenient to read the Makefile. We can put this content saved in the file as "Makefile" file, then in the directory, simply type the command "make" you can generate executable file edit. If you want to delete the executable file and all the intermediate object files, then simply execute it "make clean" on it.
In this makefile, the target file (target) contains: executable file edit and intermediate object files (*. O), dependencies (prerequisites) that those behind the colon. C files and. H files. Every one. O file has a set of dependent files, and these. O file is executable file edit the dependent files. Dependencies essentially shows which files from the target file is generated, in other words, the target file is which files updated.
After defining dependencies, subsequent line that defines how to generate the target file of the operating system commands, be sure to start with a Tab key as. Remember, make and regardless of how the command works, he just execute the defined commands. make would be more targets files and prerequisites file modification date, file date if the prerequisites file date than targets to be new, or target does not exist, then, make follow-defined command is executed.
Here we must point out that, clean is not a file, it is merely an action name, a bit like the C language lable, like its nothing after the colon, then, make it will not automatically go to file dependencies, it does not automatically execute the commands defined later. Subsequent commands to be executed, we must significantly after the make command must say this lable name. This method is useful, we can not be defined in a makefile compiler and compiler-independent or commands, such as packaged programs, backup procedures, and so on.
What is a makefile? Winodws many programmers do not know this thing, because those Windows IDE for you to do this job, but I feel the need to make a good and professional programmers, makefile to understand. It's like there are so many HTML editor, but if you want to become a professional, you still have to know HTML to identify meaning. Especially in the Unix software compiler, you can not write your own makefile, and will not write makefile, from one side shows whether a person has the ability to complete large projects.
Because, makefile relation to the entire project compilation rules. A project's source files do not count, which according to type, function, modules were placed in several directories, makefile defines a set of rules to specify which files need to be compiled, after which files need to compile, which files need to re- compile, even for more complex functions operation because makefile like a Shell scripts, which can execute operating system commands.
makefile benefits is - "Automation compilation", once written, you only need a make command, the entire project is fully automatic compilation, which greatly improves the efficiency of software development. make is a command tool is an instruction explaining the makefile command tools, in general, most of the IDE have this command, for example: Delphi's make, Visual C++ for nmake, Linux under the GNU make. Visible, makefile have become a kind of compilation methods in engineering.
In this document, will be C/C++ source code as our foundation, so inevitably involve some information about C/C++ compiler knowledge related to the content in this area, also please see the compiler documentation. Here are the default compiler is GCC under UNIX and CC.
At this point, I would like to say more about the program compiles some of the norms and methods, in general, whether it is C, C++, or pas, first of all necessary source files compiled into intermediate code file in Windows that is. Obj files, UNIX Next .o files that Object File, this action is called compilation (compile). Then put a lot of Object File synthesis executable file, this action is called link (link).
Link, mainly linked functions and global variables, so we can use these intermediate object files (O files, or OBJ files) to link our application. Linker and regardless of the source file where the function, although the function of an intermediate object files (Object File), most of the time, because too many source files, the compiler generates an intermediate object files too, and in the need to clearly point out the link among target file name, which is very convenient for the compiler, so we have to give the intermediate target pack files, in Windows, this package is called "library" (Library File), that is. lib files under UNIX, is Archive File, that is. a file.
In summary, the source file will first generate intermediate target file, and then from the middle of the target file to generate executable file. At compile time, the compiler detects only program syntax, and functions, whether the variable is declared. If the function is not declared, the compiler will give a warning, but can generate Object File. In the linker, the linker will find all of the Object File in the implementation of the function, if not, it will be reported to the link error code (Linker Error), the VC, this error is usually: Link 2001 error, saying that that the linker can not find the function implementation. You need to specify the function Object File.
Well, get, GNU's make lots of stuff, without further ado, let us begin.
Makefile describes
make command is executed, you need a Makefile to tell how to make command required to compile and link the program.
First, we use an example to illustrate the Makefile rules of writing. In order to give you a sense of Xing understanding. This example comes from the GNU make manual, in this example, we have eight C project files, header files, and 3, we write a Makefile to tell how to make command to compile and link these files. Our rules are:
1) If this project is not compiled, then we have all the C files compiled and linked.
2) If this works for a few C file is modified, then we only compile C files are modified, and link target
program
3) If the project header file is changed, then we need to compile quoted this several header files in C files and link target program.
As long as our Makefile written good enough, all of this, we only use a make command can be completed, make command automatically intelligently according to the current file modification to determine which files need to be recompiled, and thus need to compile program files and link targets.
1. Makefile rules
In about this Makefile before, let us first take a cursory look at the Makefile rules.
target ...: Prerequisites ...
command
...
...
target that is a target file, which can be Object File, it can be executed files. Can also be a label (Label), the label of this feature, in the subsequent "pseudo target" will be described in the chapter.
prerequisites that is, to generate the required files that target or targets.
command is the make command to be executed. (Arbitrary Shell Command)
This is a file dependencies, ie, target the one or more target file depends on prerequisites in the document, and its generation rules defined in the command. White said that, prerequisites, if there is more than one file is newer than the target file, then, command defined commands will be executed. This is the Makefile rules. That is the core content of the Makefile.
In the final analysis, Makefile is such a thing that seems to me also that the end of this document. Oh. Not really, this is the main line of the Makefile and the core, but not enough to write a Makefile, I will back little by little work experience combined with my coming to you slowly. Content still living. :)
2. Sample
As previously mentioned, if a project has three header files, and eight C files, we described earlier in order to complete the three rules, we Makefile would look like this below.
edit: main.o kbd.o command.o display.o /
insert.o search.o files.o utils.o
CC-O edit main.o kbd.o command.o display.o /
insert.o search.o files.o utils.o
main.o: main.c defs.h
CC-c main.c
kbd.o: kbd.c defs.h command.h
CC-c kbd.c
command.o: COMMAND.C defs.h command.h
CC - c COMMAND.C
display.o: display.c defs.h buffer.h
CC-c display.c
insert.o: insert.c defs.h buffer.h
CC-c insert.c
search.o: search.c defs . h buffer.h
CC-c search.c
files.o: modifier for defs.h buffer.h command.h
CC-c modifier for
utils.o: utils.c defs.h
CC-c utils.c
clean :
RM edit main.o kbd.o command.o display.o /
insert.o search.o files.o utils.o
Slash (/) is a newline mean. This is more convenient to read the Makefile. We can put this content saved in the file as "Makefile" file, then in the directory, simply type the command "make" you can generate executable file edit. If you want to delete the executable file and all the intermediate object files, then simply execute it "make clean" on it.
In this makefile, the target file (target) contains: executable file edit and intermediate object files (*. O), dependencies (prerequisites) that those behind the colon. C files and. H files. Every one. O file has a set of dependent files, and these. O file is executable file edit the dependent files. Dependencies essentially shows which files from the target file is generated, in other words, the target file is which files updated.
After defining dependencies, subsequent line that defines how to generate the target file of the operating system commands, be sure to start with a Tab key as. Remember, make and regardless of how the command works, he just execute the defined commands. make would be more targets files and prerequisites file modification date, file date if the prerequisites file date than targets to be new, or target does not exist, then, make follow-defined command is executed.
Here we must point out that, clean is not a file, it is merely an action name, a bit like the C language lable, like its nothing after the colon, then, make it will not automatically go to file dependencies, it does not automatically execute the commands defined later. Subsequent commands to be executed, we must significantly after the make command must say this lable name. This method is useful, we can not be defined in a makefile compiler and compiler-independent or commands, such as packaged programs, backup procedures, and so on.
No comments:
Post a Comment