ARM processor linux paging mechanism

ARM MMU supports only two page table address translation, which is mapped using three pages to meet the storage management needs 32-bit CPU

Page size supported by ARM: There are several - 1M, 64K, 4K, 1K. In the linux kernel, ARM uses a page size of 4K, 4K page size determines the virtual address reserved for low-12bit offset address. As can be seen from the figure, the index page global directory of significant digits is 12bit, two significant digits index is 8bit, page offset is 12bit.

According to ARM hardware paging mechanism, we have come to the first level global page directory has 4096, and the second level is 256, so that the second stage can have a lot of bits can be hardware used.

In the arm linux implementation, hardware paging mechanism for ARM made slightly smaller adjustments. The first-level directory retains 2048, each occupy 8 bytes (in other words, two hardware pointers to two page table); second-class hardware PTE put two tables together continuously in both PTE table back then save the corresponding Linux status information, so two entries actually have 512 (each table 256, compared with 512 two). So that each logical PTE table just takes a page.

ARM linux page table layout is as follows:

In the arch/arm/include/asm/pgtable.h, you can see the definition PTRS_PER_PTE and PTRS_PER_PTE

#define PTRS_PER_PTE        512

#define PTRS_PER_PMD        1

#define PTRS_PER_PGD        2048

Since PGD has 2048, occupies 8 bytes each, for a total need 4 * 4K, ie ARM linux the PGD actually occupied four consecutive physical page frame.